1. Field of the Invention
The present invention relates to a method for calculating a delay in a semiconductor integrated circuit and a design method using the same, more specifically, to a delay calculation method effective to be applied when an electronic computer is used to design a semiconductor integrated circuit and a design method using the same.
2. Description of the Related Art
In designing a complicated semiconductor integrated circuit, delay calculation is very important and, in order to design a high-performance semiconductor integrated circuit, a delay calculation method which performs fast processing with high accuracy is required. In addition, in designing a huger semiconductor integrated circuit, logic synthesis and optimization procedure using a computer are performed. Such procedures require a delay calculation method which performs fast processing with high accuracy.
A total load capacitance has been generally used to calculate a cell delay in such an optimization procedure. In other words, it is a method for calculating a cell delay using a value obtained by summing all capacitance values connected to an output pin.
The technique for processing a semiconductor integrated circuit has been made finer. As a result, there is synergy between an increase in cell drivability and an increase in interconnect resistance so as to increase a xe2x80x9cshield effectxe2x80x9d in which the load capacitance of an output pin appears to be smaller than the total load capacitance. The prior art delay calculation method using a total load capacitance causes a large error.
To consider this shield effect, a method for replacing a load by one effective capacitance is known. This is discussed in detail in 15.6.1 to 15.6.4 of Proceeding Custom Integrated Circuit Conference, 1992.
However, the prior art method for replacing a load by one effective capacitance to calculate a delay is a calculation method limiting to a xcfx80-model load. A general load cannot be calculated directly.
In addition, the prior art method for replacing a load by one effective capacitance to calculate a delay is not given sufficient consideration to fast processing, and is inapplicable to a procedure for enormously executing a delay calculation procedure such as an optimization procedure.
In this way, since the shield effect cannot be considered in the prior art optimization procedure, accurate optimization has not been done for accuracy.
Accordingly, a first object of the present invention is to provide a delay calculation method which can calculate an effective capacitance using a general load form.
In addition, a second object of the present invention is to provide a delay calculation method which permits fast processing.
Further, a third object of the present invention is to provide a design method of a semiconductor integrated circuit using an optimization procedure of the delay calculation method which performs fast processing with high accuracy.
To achieve the first object, a delay calculation method according to the present invention of a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires, in which a circuit connected to the output pin of an electronic circuit cell is replaced by one effective capacitance to calculate a delay in the electronic circuit cell, the delay calculation method, as described later using FIG. 1, comprises, after a circuit connected to the output pin is expressed by an equivalent circuit including resistances and capacitances or inductances, procedure 101 which calculates transition time until voltage of the output pin reaches a definition voltage for delay, procedure 102 which calculates voltage of capacitance node of the equivalent circuit at the transition time, procedure 103 which calculates the effective capacitance from the voltage of capacitance node, and procedure 104 which calculates a delay in the electronic circuit cell from the effective capacitance.
To achieve the second object, a delay calculation method according to the present invention of a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires, in which a circuit connected to the output pin of an electronic circuit cell is replaced by one effective capacitance to calculate a delay in the electronic circuit cell, the delay calculation method, as described later using FIG. 2, comprises, after a circuit connected to the output pin is expressed by an equivalent circuit including resistances and capacitances or inductances, procedure 201 which calculates output transition time until voltage of the output pin reaches the definition voltage for delay, procedure 202 which calculates capacitance node transition time until voltage of capacitance node in the equivalent circuit reaches the definition voltage for delay, procedure 203 which calculates the effective capacitance from the output transition time and the capacitance node transition time, and procedure 204 which calculates a delay in the electronic circuit cell from the effective capacitance.
To achieve the third object, a design method of a semiconductor integrated circuit having a plurality of electronic circuit cells, as described later using FIG. 9, comprises delay calculation procedure 901 which calculates a delay in the electronic circuit cell, judgment procedure 902 which judges whether desired conditions are met, and cell modification procedure 903 which modifies the type or a combination of the electronic circuits, in which the type or a combination of the electronic circuit cells is selected so as to meet the desired conditions,
the design method wherein
the delay calculation procedure 901 uses the delay calculation method using the effective capacitance calculation method.
In the delay calculation method of a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires, an interconnect delay calculation method comprises a first procedure which calculates output transition time TT1 of the cell from total load capacitance Ct obtained by summing capacitance values connected to the output of the electronic circuit cell, a second procedure which calculates temporary interconnect delay Tw0 from interconnect resistance Rw and interconnect capacitance Cw of the wire connected to the electronic circuit cell and input capacitance Cci of the electronic circuit cell as a load connected, and a third procedure which calculates interconnect delay Tw from the output transition time TT1 and the temporary interconnect delay Tw0 by the following expression:
Tw=Tw0xc2x7[1xe2x88x92exp{xe2x88x92(a1xc2x7Tw0+a2xc2x7TT1)/Tw0}]
In the delay calculation method of a semiconductor integrated circuit having a plurality of electronic circuit cells and a plurality of wires, an interconnect delay calculation method comprises a first procedure which calculates output transition time TT1 of the cell from total load capacitance Ct obtained by summing capacitance values connected to the output of the electronic circuit cell, a second procedure which calculates output transition time TT2 of the cell from effective capacitance Ceff effective as output load capacitance of the electronic circuit cell, a third procedure which calculates temporary interconnect delay Tw0 from interconnect resistance Rw and interconnect capacitance Cw of the wire connected to the electronic circuit cell and input capacitance Cci of the electronic circuit cell as a load connected, and a fourth procedure which calculates interconnect delay Tw from the output transition time TT1, the output transition time TT2, and the temporary interconnect delay Tw0 by the following equation:
Tw=Tw0+(b1xc2x7TT1xe2x88x92b2xc2x7TT2xe2x88x92Tw0)xc2x7exp{xe2x88x92(b3xc2x7Tw0+b4xc2x7TT1)/Tw0}
The foregoing objects and other objects of the present invention will be apparent by the following detailed description and the appended claims with reference to the accompanying drawings. In the accompanying drawings, like or similar parts are identified by the same reference numerals.